The present invention relates to a structure and a process for fabrication of a semiconductor device including a metal conductive element, in particular to a structure and process for fabrication of a floating gate in a flash memory device.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions.
However, due to complex process technologies used in fabrication of state of the art flash memories, further improvement of memory density has become more challenging.
A floating gate flash memory device includes a floating gate electrode upon which electrical charge is stored. The floating gate electrode is formed on a tunnel oxide layer which overlies a channel region residing between the source and drain regions in a semiconductor substrate. The floating gate electrode together with the source and drain regions form an enhancement transistor. Typically, the floating gate electrode has been formed of polysilicon. Metal floating gates have also been used.
Referring to FIG. 1, there is schematically shown in cross-section a conventional floating gate flash memory device or cell 10 suitable for use in a floating gate flash EEPROM device. The cell 10 includes source/drain regions 12 and 14 located in a semiconductor substrate 16. The source and drain regions 12 and 14 are separated by a channel region 18. A xe2x80x9ctunnelxe2x80x9d or bottom dielectric material layer 20 overlies the source and drain regions 12 and 14 and the channel region 18. A floating gate electrode 22 overlies the tunnel dielectric layer 20. The floating gate electrode 22 may be polysilicon or polysilicon-germanium, a metal or a silicide, for example. The floating gate electrode 22 is separated from a control gate electrode 26 by an interlayer dielectric layer 24. The control gate electrode 26, the interlayer dielectric 24 and the floating gate electrode 22 form a floating gate flash memory cell structure, which may be referred to as a stack gate.
It should be noted that the floating-gate flash memory cell 10 is a symmetrical device. Therefore, the use of the terms xe2x80x9csourcexe2x80x9d and xe2x80x9cdrain,xe2x80x9d as they are commonly used with conventional transistor devices, may be confusing. For example, each floating gate flash memory cell 10 comprises a pair of adjacent source/drain regions 12, 14. During program, erase and read functions, one of these two source/drain regions 12/14 will serve as a source, while the other will serve as a drain. In conventional transistor terminology, electrons travel from the source to the drain. Which of the source/drain regions 12/14 functions as a source, and which of the source/drain regions 12/14 functions as a drain, depends on the function being performed and on the manner in which the floating gate 22 is being addressed (i.e., whether it is being programmed, erased or read). Thus, it is to be understood that references to source or drain may refer to different structures at different times.
In a floating gate flash memory device, electrons are transferred to the floating gate electrode 22 through the tunnel dielectric layer 20 overlying the channel region 18 of the floating gate flash memory cell 10. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating gate electrode 22 by the overlying control gate electrode 26. The control gate electrode 26 is capacitively coupled to the floating gate electrode 22, such that a voltage applied on the control gate electrode 26 is coupled to the floating gate electrode 22 through the interlayer dielectric layer 24, which may be referred to as the interpoly dielectric when both the floating gate and the control gate are formed of or comprise polysilicon. The floating gate flash memory device 10 is programmed by applying a high positive voltage to the control gate electrode 26, and a lower positive voltage to the drain region 14, which transfers electrons from the channel region 18 to the floating gate electrode 22. Electron injection carries negative charge into the floating gate. This injection mechanism is normally induced by grounding the source region 12 and a bulk portion of the substrate 16, applying a relatively high positive voltage to the control gate electrode 26, for example, +12 Volts (V), to create an electron attracting field and applying a positive voltage of moderate magnitude (i.e., approximately +6 V to +9 V) to the drain region 14 in order to generate xe2x80x9chotxe2x80x9d (high energy) electrons. After sufficient negative charge accumulates on the floating gate 22, the negative potential of the floating gate 22 raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region 18 during a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether an EEPROM cell is programmed or not. Typically, in the read mode, a relatively low positive voltage, for example, +1.5 V, is applied to the drain region 14, +5 V is applied to the control gate electrode 26 and 0 V is applied to the source region 12 of the floating gate flash memory cell 10.
The act of discharging the floating gate 22 is called the erase function for a flash EEPROM cell. This erasure function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate 22 and the source region 12 of the transistor (source erase or negative gate erase) or between the floating gate 22 and the substrate 16 via the channel region 18 (channel erase). The xe2x80x9cflashxe2x80x9d EEPROM derives its name from the feature that all of the cells in a row can be erased at once.
One concern with floating gate flash memories is variation in Vt, the threshold voltage of the floating gate cell. For example, if the target Vt is 3 v, the range of actual Vt observed may be from 2.7 v to 3.3 v. This is undesirable, since such variation creates uncertainty as to the program state of the cell. Conventional floating gate cells use lightly doped polysilicon as the charge storage medium. If the doping is non-uniform, the non-uniformity can increase the range of Vt, and there may be a voltage drop across the floating gate if the doping level is too low. In addition, there is the problem of the depletion effect which may be observed in semiconductor materials such as polysilicon. Such problems may be avoided by use of a metal floating gate.
A second concern with floating gate flash memories is the work function of the floating gate material, and the energy barrier height which must be overcome by electrons during programming, reading and erasing floating gate cells.
A continuing concern in the industry is reduction of size and increase in density of components of semiconductor devices, and in particular, in flash memory devices. One way to increase higher density of programmable/erasable memory bits is to minimize the memory cell pitch. However, the present limits of lithography have been encountered in the drive towards ever-smaller and more densely packed memory cells. Thus, numerous challenges remain in the fabrication of material layers for use in flash memory devices. What is needed in the art is a process which allows for fabrication of flash memory device elements at the smallest possible dimensions. Reduction of the size of the central elements of such devices is a needed component of such improvements. Such size reduction should also be accompanied by improvements in the quality of the elements, since the tolerance for error and impurities is reduced even faster than the desired reductions in size and increases in density.
Thus, what is needed is a process for fabrication of a floating gate flash memory device which provides both size reduction and maintenance or improvement of the quality of the elements of the device.
The present invention relates to processes for forming floating gate flash memory devices having reduced size and increased performance, which address the problems of the prior art. In one embodiment, the present invention relates to a process for fabrication of a floating gate flash memory device including steps of providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; forming a reverse tunnel dielectric layer in the reduced trench; and filling the reduced trench with a floating gate material.
In another embodiment, the present invention relates to a process for fabrication of a floating gate flash memory device including steps of providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; and filling the reduced trench with a metal floating gate material.
In still another embodiment, the present invention relates to a process for fabrication of a floating gate flash memory device including steps of providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; depositing a barrier layer in the initial trench; and filling the reduced trench with a metal floating gate material.
In yet another embodiment, the present invention relates to a process for fabrication of a floating gate flash memory device including steps of providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer and the pad dielectric layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; forming a reverse tunnel dielectric layer in the reduced trench; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lr1; and filling the reduced trench with a metal floating gate material.
In one embodiment, these processes further includes a step of etching to form a stack gate comprising a floating gate and a spacer formed from a portion of the hard mask layer.
The present invention further relates to devices fabricated in accordance with the foregoing processes. In one embodiment, the present invention relates to a floating gate flash memory device including: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a reverse tunnel dielectric layer; c) a stack gate comprising a floating gate electrode, hard mask spacers, and at least one of sidewall/spacers, second sidewalls or a barrier layer, wherein the floating gate is positioned above the channel region, with the floating gate separated from the hard mask spacers by the at least one of sidewall/spacers, second sidewalls or a barrier layer, wherein the floating gate is separated from the channel region by the reverse tunnel dielectric layer; and d) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer.
In another embodiment, the present invention relates to a floating gate flash memory device including: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a stack gate comprising a metal floating gate electrode, hard mask spacers, sidewall/spacers and a barrier layer, wherein the barrier layer includes sidewalls adjacent the metal floating gate, the sidewall/spacers are between the metal floating gate and the hard mask spacers, the metal floating gate is positioned above the barrier layer and the stack gate is separated from the channel region by a pad dielectric layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer.
In still another embodiment, the present invention relates to a floating gate flash memory device including: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a stack gate comprising a metal floating gate electrode, hard mask spacers and a barrier layer, wherein the barrier layer includes sidewalls separating the metal floating gate from the hard mask spacers, the metal floating gate is positioned above the barrier layer and the stack gate is separated from the channel region by a pad dielectric layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer.
In yet another embodiment, the present invention relates to a floating gate flash memory device including: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a reverse tunnel dielectric layer; c) a stack gate comprising a metal floating gate electrode, hard mask spacers, and a barrier layer, wherein the barrier layer includes sidewalls separating the metal floating gate from the hard mask spacers, the metal floating gate is positioned above the barrier layer and the stack gate is separated from the channel region by the reverse tunnel dielectric layer; and d) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer.
Thus, in the present invention, by use of a floating gate, which in some embodiments is a metal floating gate, having its size reduced by addition of sidewalls and/or a barrier layer, a floating gate flash memory device may be fabricated including a floating gate having reduced dimensions by a process which can be easily implemented into current process flows without introducing extensive new equipment, thus achieving a cost reduction or avoiding a cost increase, while increasing the production yield and memory density. The present invention provides for advantages such as (1) reduced memory cell dimensions; (2) easy incorporation into existing processes; (3) improved data retention and reliability in flash memory cells; and (4) avoiding of increased costs in achieving improved performance in smaller memory cells. Thus, the present invention provides an advance in memory storage layer fabrication technology for floating gate flash memory devices, and ensures proper charge retention, while at the same time providing distinct process and economic advantages.
Although described herein in terms of a floating gate flash memory device, the present invention is broadly applicable to fabrication of any semiconductor device that includes a metal structure having reduced dimensions or to any other floating gate flash memory device.